The present invention relates to a semiconductor memory device, and more particularly, to a method for driving a word line by decoding an address.
A semiconductor memory device includes a plurality of cell blocks therein, and each of the cell blocks includes a plurality of memory cells. In a case where the number of word lines in each cell block is a power of 2, e.g., 256 or 512, it is relatively simple to select a word line to be driven according to an address. If the cell block includes 256 word lines, eight addresses are used to select the word line that corresponds to the address one-to-one; and if the cell block includes 512 word lines, nine addresses are used to select the word line that corresponds to the address one-to-one. However, a semiconductor memory device may be designed in a configuration that the number of word lines provided in each cell block is not a power of 2. For example, when the cell block includes 512 word lines, the efficiency in current consumption and timings may be degraded due to a large size of the cell block. However, when the cell block includes 256 word lines, the number of data stored in one cell block decreases, which leads to an increase in the total number of the cell blocks. Accordingly, the memory device is often designed in such a manner that the number of word lines is not a power of 2, for example, the number of word lines provided in each cell block is 384.
In this case, because the number of word lines to be selected in each of the cell blocks does not one-to-one correspond to the number of addresses, a procedure of selecting a word line becomes complicated. This will be described in detail below.
FIG. 1 is a block diagram of a conventional semiconductor memory device having a circuit configuration for selecting a word line by decoding an address.
As shown, the conventional semiconductor memory device includes eleven cell blocks 120 to 220 each of which is provided with 384 word lines, and a pre-decoder 110. That is, the total number of the word lines is 4,224. The pre-decoder 110 pre-decodes seventh to eleventh addresses X<7:11> to output addresses PMS<0:10>. The addresses PMS<0:10> only change their forms from the seventh to eleventh addresses X<7:11>, but are also similar to the seventh to eleventh address addresses X<7:11>. Although not shown, addresses other than the addresses PMS<0:10> are also inputted to each of the cell blocks 120 to 220.
The addresses outputted form the pre-decoder 110 and the other addresses not shown herein are inputted to each of the cell blocks 120 to 220, and control a main word line driving unit 121, a phi X driving unit 124, a sub word line driving unit 127, and the like to drive a specific word line selected by the address.
FIG. 2 is a mapping table illustrating the mapping relationship between the cell blocks and the addresses X<7:11>. The cell blocks are respectively selected by combinations of the addresses as illustrated in FIG. 2. Since one of the eleven cell blocks is selected using five addresses, some cell blocks, e.g., the zeroth to ninth cell blocks, are selected by three combinations of the five addresses, and other cell blocks, e.g., the tenth cell block, is selected by two combinations of the five addresses.
FIGS. 3 to 6 are circuit diagrams exemplarily illustrating how addresses are decoded in the pre-decoder 110 shown in FIG. 1.
Referring to FIG. 3, a reference symbol ‘BXA7’ indicates a seventh address, and a reference symbol ‘BXA8’ indicates an eighth address. A reference symbol ‘AXI<70>’ is a signal having a value of ‘1’ when both the seventh and eighth addresses BXA7 and BXA8 have values of ‘0’, and a reference symbol ‘AXI<73>’ is a signal having a value of ‘1’ when both seventh and eighth addresses BXA7 and BXA8 have values of ‘1’. Likewise, although not shown, a reference symbol ‘AXI<71>’ is a signal having a value of ‘1’ when the seventh address BXA7 has a value of ‘1’ and the eighth address BXA8 has a value of ‘0’, and a reference symbol ‘AXI<72>’ is a signal having a value of ‘1’ when the seventh address BXA7 has a value of ‘0’ and the eighth address BXA8 has a value of ‘1’. A reference symbol ‘BXA8B’ indicates merely an inverted signal of the eighth address BXA8, a reference symbol ‘AXBI<70>’ indicates merely an inverted signal of the signal AXI<70>, and a reference symbol ‘AXBI<73>’ indicates merely an inverted signal of the signal AXI<73>.
That is, the addresses AXI<70>, BXA8B and AXI<73> are obtained by pre-decoding the respective addresses. The addresses AXI<XX>, which are pre-decoded in this manner, are used in various kinds of blocks, which will be described later.
Referring to FIG. 4, ninth to eleventh addresses BXA9, BXA10 and BXA11 are pre-decoded to generate addresses MMS<0:7>. The addresses MMS<0:7> are binary codes obtained by transforming the ninth to eleventh addresses BXA9, BXA10 and BXA11 into binary numbers. When all the ninth to eleventh addresses BXA9, BXA10 and BXA11 have values of ‘0’, the address MMS<0> has a value of ‘1’; and when all the ninth to eleventh addresses BXA9, BXA10 and BXA11 have values of ‘1’, the address MMS<7> has a value of ‘1’. The addresses MMS<0:7> change their forms from the addresses BXA9, BXA10 and BXA11, but they are also addresses, which will be used in various kinds of blocks to be described later.
Referring to FIG. 5, it can be seen that addresses PMS<0:3> are generated through decoding the pre-decoded addresses MMS<X> and AXBI<X>. Each of the addresses PMS<0:3> is a signal activated when each of the cell blocks <0:3> is selected. This can be understood from the addresses used to generate the addresses PMS<0:3> and the mapping table of FIG. 2. Although not shown, addresses PMS<4:7> may be generated in the same manner as the addresses PMS<0:3>. A reference symbol ‘R3DI’ indicates a signal used in a test mode for testing a redundancy cell, and is fixed to a value of ‘1’ during a normal operation.
Referring to FIG. 6, it can be seen that addresses PMS<8:10> are generated by decoding the address MMS<X> and the address AXBI<X>. The addresses PMS<8:10> are activated when each of the cell blocks <8:10> is selected, which can be understood from the mapping table of FIG. 2.
FIGS. 7 and 8 are circuit diagrams of the main word line driving unit 121 shown in FIG. 1. FIG. 7 illustrates a portion of the main word line driving unit 121 receiving addresses. To be specific, FIG. 7 illustrates the portion of the main word line driving unit 121 provided in the zeroth cell block 120, and therefore, the main word line driving unit 121 is enabled by the address PMS<0>. This is because the address PMS<0> is activated when the zeroth cell block 120 is selected.
That is, the circuit of FIG. 7 generates signals MWDI<60:65> which are activated to logic ‘low’ according to which address is activated among the addresses AXI<60:65> during an activation of the address PMS<0>. The addresses AXI<60:65> are obtained by decoding the sixth to eighth addresses BXA6, BXA7 and BXA8. The circuit of FIG. 7 is provided in plurality in the main word line driving unit 121 depending on the number of word lines to be driven.
FIG. 8 illustrates another portion of the main word line driving unit 121 for driving a zeroth main word line MWLB<0> based on the combination of the signal MWDI<60> and the address AXI<30>. When the address AXI<30>, which is achieved based on the combination of third to fifth addresses, is activated to logic ‘high’ in a state that the signal MWDI<60> is activated to logic ‘low’, the zeroth main word line MWLB<0> is enabled to logic ‘low’. The other main word lines, i.e., main word lines other than the zeroth main word line MWLB<0>, are also enabled based on the combination of the respective addresses in the same manner as the zeroth main word line MWLB<0>. A reference symbol ‘WPHMW’ indicates a control signal of the main word line driving unit 121, which is irrespective of a procedure of selecting the word line.
FIGS. 9 and 10 are circuit diagrams of the phi X driving unit 124 shown in FIG. 1. FIG. 9 illustrates a portion of the phi X driving unit 124 receiving addresses. Similarly to the main word line driving unit 121, the phi X driving unit 124 is also enabled based on the address PMS<0> because the phi X driving unit 124 is also provided in the zeroth cell block 120. The phi X driving unit 124 generates a signal FXD20 and a signal FXD21 which are activated to logic ‘low’ based on the combination of the addresses AXI<20:21> that are obtained based on the combination of the second to fourth addresses.
FIG. 10 illustrates another portion of the phi X driving unit 124 generating a zeroth phi X control signal FXB<0>. The zeroth phi X control signal FXB<0> is activated to logic ‘low’ when the zeroth address AXI<0> has a value of ‘1’ in a state that the signal FXD20 generated in the portion of the phi X driving unit 124 in FIG. 9 is activated to logic ‘low’. The other phi X control signals are also activated in the same manner as the zeroth phi X control signal FXB<0> based on the combination of the respective addresses. A reference symbol ‘WPHFX’ indicates a control signal of the phi X driving unit 124, which is irrespective of a procedure of selecting the word line.
FIG. 11 is a circuit diagram of the sub word line driving unit 127 shown in FIG. 1. To be specific, FIG. 11 illustrates a portion of the sub word line driving unit 127, which drives zeroth, second, fourth, sixth, eighth, tenth, twelfth and fourteenth sub word lines SWL0, SWL2, SWL4, SWL6, SWL8, SWL10 and SWL12 controlled by the zeroth main word line MWLB0. Each sub word line SWL is enabled to logic ‘high’ when the corresponding main word line MWLB and the corresponding phi X control signal FXB are activated to logic ‘low’.
If the number of word lines provided in each cell block is not a power of 2, the addresses and the word lines do not correspond to each other one-to-one. Therefore, some addresses should perform selecting the word line in the cell block and selecting the cell block concurrently.
A plurality of control circuits controlling a decoder are required to perform the sequential selection operation because the selection of the word line in the cell block and the selection of the cell block are performed concurrently. This causes the main word driving unit, the phi X driving unit, and so forth to have complex configurations.
In particular, the signal PMS<0:10> for selecting the cell block can be produced after passing through a plurality of decoding terminals, leading to a delay during this procedure. After the generation of the signal PMS<0:10> selecting the cell block, a subsequent decoding operation (word line selecting operation) is performed to select the word line of the cell block in a state that the word line driving unit and the phi X driving unit in the cell block are enabled by the generated signal PMS<0:10>. Therefore, the time delay increases. If the time taken for the word line to be selected and enabled increases as above, there is a problem that a sensing margin of a sense amplifier and AC characteristic (e.g., tRCD and tRP) may be deteriorated.
Moreover, a total area for circuits for decoding the word line is large, which leads to an increase in current consumption and layout area.